This invention relates generally to nonvolatile memories and particularly to electrically erasable nonvolatile memories.
Nonvolatile memory cells are advantageous since they retain recorded information even when the power to the memory is turned off. There are several different types of nonvolatile memories including erasable programmable read only memories (EPROMs), electrically erasable and programmable read only memories (EEPROMs) and flash EEPROM memories. EPROMs are erasable through light exposure but are electrically programmable by channel hot electron injection onto a floating gate. Conventional EEPROMs have the same programming functionality, but instead of being light erasable they can be erased and programmed by electron tunneling. Thus, information may be stored in these memories, retained when the power is off, and the memories may be erased for reprogramming, as necessary, using appropriate techniques. Flash EEPROMs may be block erased, typically giving them better read access times than regular EEPROMs.
Currently, flash memories have gained considerable popularity. For example, flash memories are often utilized to provide on-chip memory for microcontrollers, modems and SMART cards and the like where it is desirable to store codes that may need fast updating.
While flash memories and EEPROMs are closely related, in many instances, flash memories are preferred because their smaller cell size means that they can be made more economically. However, flash memories and EEPROMs often have very similar cell attributes.
Particularly with an EEPROM, the electrical programming of the cells normally requires substantial potentials to be applied to the cells. These potentials induce electron tunneling from an N+ region onto the floating gate. Additional complexity may arise from the need to provide substantially larger voltages to memory cells than are needed for normal transistor operation.
Furthermore, with the conventional flash EEPROMs, the electrical programming of the cells normally requires high current to be applied to the cells. A very minute amount of this electron current becomes injected from the drain depletion region onto the floating gate. This means that the injection efficiency of such devices is low (e.g., 1.times.10.sup.-6 to 1.times.10.sup.-9). The requirement of high current adds additional complexity because of the design of the high current pump operated at low voltage.
While the industry has come to appreciate that significant voltages are needed to program EEPROMs and significant currents to program flash EEPROMs, there would be a substantial demand for a nonvolatile memory which was both electrically erasable and programmable without the need for relatively higher programming voltages and higher currents.
In many applications, it is desirable for the memory array to be compact so as to increase the number of devices incorporated into a given topology. This can result in decreased size and cost and in some cases higher access speeds. In such compact applications, it may be acceptable to use a process for making the memory arrays that is not compatible with the processes used to make logic devices, because the arrays are formed on a chip that is separate from the logic chip. Thus, it is also desirable, in some situations, to have a compact memory call that also achieves lower programming voltages or currents.